Calibration of pipeline ADC with pruned Volterra kernels

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1-2.5 bits (6-15 dB) with 37101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 mm2 , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively

Subsampling models of bandwidth mismatch for time-interleaved converter calibration

Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two previously published calibration algorithms for the correction of bandwidth mismatch is shown. The proposed models can thus be used to simulate subsampling TI-ADCs and their calibration algorithms

A distortion model for pipeline analog-to-digital converters

Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderately high sampling frequency. In typical implementations, linearity is often limited by capacitor mismatch and finite amplifier gain. The impact of these non ideal effects on the overall linearity of the ADC has been addressed in this paper, obtaining a model to estimate total harmonic distortion (THD), given capacitors' sizing and amplifiers' gain. This model enables the designer to analyze the impact of error sources in each stage separately, and to perform Monte Carlo simulations. In this way, design rules can be obtained to properly size each multiplying digital-to-analog converter (MDAC) in the first stages of the design process

A class-AB very low voltage amplifier and sample & hold circuit

In this paper we present a low-power low-voltage class-AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain of one and two: as the latter is the basic stage of a Multiplying DAC (MDAC), the proposed amplifier may be used to obtain a low-voltage low-power pipeline Analog-to-Digital Converter (ADC). The design has been validated by simulations using the technology models of the STMicroelectronics 65nm CMOS process. The two-stage amplifier has a gain of 26dB at 0.5V, which increases up to 37dB at 1.0V, and a unity gain frequency of 14MHz when supplied at 0.5V, which increases beyond 1GHz at 1.0V. The two SHAs can work at up to 5MSps with a 0.5V supply and consume less than 2μW, showing a THD of -56dB throughout the Nyquist band. Higher sampling frequencies can be obtained increasing the supply voltage and power consumption. © 2011 IEEE

Digital background calibration of subsampling time-interleaved ADCs

A technique for the digital background calibration of subsampling time-interleaved analog-to-digital converters is proposed. The technique corrects the errors due to gain, offset and timing mismatches among the time-interleaved channels by estimating and nulling the errors with respect to a reference channel through least mean squares loops. Wideband undersampled differentiator filters are exploited thus enabling digital background calibration of timing skews even with wideband input signals outside the first Nyquist band

Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters

In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a 0.13-mu m CMOS technology show an accuracy of the model as high as 17 bits

Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters

We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conversion, even in the presence of wideband input signals and signals beyond the first Nyquist band. The proposed algorithm improves a previous work by the authors by allowing higher precision, particularly in the case of many interleaved channels and large mismatches. Accuracy improves by 3-8 bits with respect to the previous algorithm and up to 10 bits with respect to the uncalibrated case

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band